`timescale 1ns/100ps

module tb_myand();

    reg [1:0] in;
    wire out;

    myand u_myand
    (
        
        .a(in[0]), 
        .b(in[1]),
        .c(out)
    );

    initial begin
        $dumpfile("wave.vcd"); //生成的vcd文件名称
        $dumpvars(0, tb_myand); //tb模块名称
    end

    initial begin
        in <= 2'b00;
        #10
        in <= 2'b01;
        #10
        in <= 2'b10;
        #10
        in <= 2'b11;
        #10
        in <= 2'b00;
        #10
        in <= 2'b01;
        #10
        in <= 2'b10;
        #10
        in <= 2'b11;
        #10
        $stop;
    end

endmodule





